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HIGH-SPEED 2K x 8 FourPortTM STATIC RAM
Features
x
IDT7052S/L
x
x
x
x
x
High-speed access - Military: 25/35ns (max.) - Commercial: 20/25/35ns (max.) Low-power operation - IDT7052S Active: 750mW (typ.) Standby: 7.5mW (typ.) - IDT7052L Active: 750mW (typ.) Standby: 1.5mW (typ.) True FourPort memory cells which allow simultaneous access of the same memory locations Fully asynchronous operation from each of the four ports: P1, P2, P3, P4 Versatile control for write-inhibit: separate BUSY input to control write-inhibit for each of the four ports Battery backup operation--2V data retention
x x
x x
TTL-compatible; single 5V (10%) power supply Available in 120 pin and 132 pin Thin Quad Flatpacks and 108 pin PGA Military product compliant to MIL-PRF-38535 QML Industrial temperature range (-40C to +85C) is available for selected speeds
Description
The IDT7052 is a high-speed 2K x 8 FourPortTM Static RAM designed to be used in systems where multiple access into a common RAM is required. This FourPort Static RAM offers increased system performance in multiprocessor systems that have a need to communicate in real time and also offers added benefit for high-speed systems in which multiple access is required in the same cycle. The IDT7052 is also designed to be used in systems where on-chip hardware port arbitration is not needed. This part lends itself to those
Functional Block Diagram
R/WP1 CEP1 OEP1 I/O0P1-I/O7P1 BUSYP1 PORT 1 ADDRESS DECODE LOGIC PORT 2 ADDRESS DECODE LOGIC PORT 4 ADDRESS DECODE LOGIC PORT 3 ADDRESS DECODE LOGIC COLUMN I/O COLUMN I/O R/WP4 CEP4 OEP4 I/O0P4-I/O7P4 BUSYP4
A0P1 - A10P1
A0P4 - A10P4
MEMORY ARRAY
A0P2 - A10P2
A0P3 - A10P3
BUSYP2 I/O0P2-I/O7P2 OEP2 CEP2 R/WP2 COLUMN I/O COLUMN I/O
BUSYP3 I/O0P3-I/O7P3 OEP3 CEP3 R/WP3
2674 drw 01
JUNE 1999
1
(c)1999 Integrated Device Technology, Inc. DSC 2674/9
IDT7052S/L High-Speed 2K x 8 FourPortTM Static RAM
Military, Industrial and Commercial Temperature Ranges
systems which cannot tolerate wait states or are designed to be able to externally arbitrate or withstand contention when all ports simultaneously access the same FourPort RAM location. The IDT7052 provides four independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. It is the user's responsibility to ensure data integrity when simultaneously accessing the same memory location from all ports. An automatic power down feature, controlled by CE, permits the on-chip circuitry of each port to enter a very low power standby power mode.
Fabricated using IDT's CMOS high-performance technology, this FourPort SRAM typically operates on only 750mW of power. Low-power (L) versions offer battery backup data retention capability, with each port typically consuming 50W from a 2V battery. The IDT7052 is packaged in a ceramic 108-pin Pin Grid Array (PGA), 120-pin Thin Quad Flatpack (TQFP) and 132-pin Plastic Quad Flatpack (PQF). Military grade product is manufactured in compliance with the latest revision of MIL-PRF-38535 QML, making it ideally suited to military temperature applications demanding the highest level of performance and reliability.
Pin Configurations(1,2,3)
81 80 77 74 72 69 68 65 63 60 57 54
R/W P2
84 83
NC
78
A7 P2
76
A5 P2
73
A3 P2
70
A0 P2
67
A0 P3
64
A3 P3
61
A5 P3
59
A7 P3 A8 P3
55
NC
56
R/W P3
53
12
BUSY P2
87 86
OE P2
82
A8 P2
79
A10 P2
75
A4 P2
71
A1 P2
66
A1 P3
62
A4 P3 A6 P3
A10 P3
58
OE P3
51
BUSY P3
50
11
A2 P1
90 88
A1 P1
85
CE
A9 P2
A6 P2
A2 P2
A2 P3
A9 P3
52
CE P3
49
A1 P4
47
A2 P4 A5 P4
45
10
A5 P1
92 91
A3 P1
89
A0 P1
48
A0 P4
46
A3 P4 A6 P4
43 42
09
A10 P1
95 94
A6 P1
93
A4 P1
44
A4 P4 GND
39 40
A10 P4 A8 P4
41
08
A8 P1
96 97
A7 P1 NC
100
VCC
98
IDT7052G G108-1(4) 108-Pin PGA Top View(5)
A7 P4 NC
37 38
07
A9 P1
99
CE P1
102
CE P4
35
A9 P4 R/W P4
36
06
R/W P1
101
OE P1
103
I/O0 P1
106
GND
31
OE P4
34
05
BUSY P1
104
I/O1 P1
105 1
GND
4 8 12 17 21 25
GND
28 32
I/O7 P4 I/O5 P4
29
BUSY P4
33
04
I/O2 P1
107 2
I/O3 P1
5
I/O6 P1
7
VCC
GND
10
VCC
13
VCC
16
GND
19
VCC
22
I/O2 P4
24
I/O6 P4
30
03
I/O4 P1
108 3
I/O7 P1
6
I/O0 P2
9
I/O2 P2 I/O3 P2 D
I/O4 P2
11
I/O6 P2
14 15
I/O1 P3 I/O0 P3 G
I/O3 P3
18
I/O5 P3
20 23
I/O7 P3 I/O6 P3 K
I/O3 P4
26
I/O4 P4
27
02
I/O5 P1 A INDEX
NC B
I/O1 P2 C
I/O5 P2 E
I/O7 P2 F
I/O2 P3 H
I/O4 P3 J
I/O0 P4 L
I/O1 P4 M
2674 drw 02
01
NOTES: 1. All VCC pins must be connected to the power supply. 2. All GND pins must be connected to the ground supply. 3. Package body is approximately 1.21 in x 1.21 in x .16 in. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking.
2 6.42
IDT7052S/L High-Speed 2K x 8 FourPortTM Static RAM
Military, Industrial and Commercial Temperature Ranges
Pin Configurations(1,2,3) (con't.)
17 18
N/C OEP2 BUSYP2 N/C A0P1 A1P1 A2P1 A3P1 A4P1 A5P1 A6P1 N/C A10P1 VCC A7P1 A8P1 A9P1 N/C CEP1 R/WP1 OEP1 BUSYP1 N/C I/O0P1 I/O1P1 I/O2P1 I/O3P1 GND N/C I/O4P1 I/O5P1 N/C N/C
N/C CEP2 R/WP2 N/C A9P2 A8P2 A7P2 A10P2 N/C A6P2 A5P2 A4P2 A3P2 A2P2 A1P2 A0P2 N/C A0P3 A1P3 A2P3 A3P3 A4P3 A5P3 A6P3 A10P3 A7P3 A8P3 A9P3 N/C OEP3 CEP3 R/WP3 N/C
1 117 116
IDT7052PQF PQ132-1(4) 132-Pin Plastic Quad Flatpack Top View(5,6)
50 51 83
84
N/C BUSYP3 N/C A0P4 A1P4 A2P4 A3P4 A4P4 A5P4 A6P4 N/C A10P4 GND A7P4 A8P4 A9P4 N/C CEP4 R/WP4 OEP4 BUSYP4 N/C GND N/C I/O7P4 I/O6P4 I/O5P4 GND I/O4P4 I/O3P4 I/O2P4 N/C N/C
N/C I/O6P1 I/O7P1 N/C VCC N/C I/O0P2 I/O1P2 I/O2P2 GND I/O3P2 I/O4P2 I/O5P2 VCC I/O6P2 I/O7P2 N/C I/O0P3 I/O1P3 VCC I/O2P3 I/O3P3 I/O4P3 GND N/C I/O5P3 I/O6P3 I/O7P3 N/C VCC I/O0P4 I/O1P4 N/C
2674 drw 03
NOTES: 1. All VCC pins must be connected to the power supply. 2. All GND pins must be connected to the ground supply. 3. PQ132-1 package body is approximately .95 in x .95 in x .14 in. PN120-1 package body is approximately 14mm x 14mm x 1.4mm. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking 6. The side of the package containing pin1 may have a bevelled edge in place of the indicator dot..
N/C I/O6P1 I/O7P1 N/C VCC I/O0P2 I/O1P2 I/O2P2 GND I/O3P2 I/O4P2 I/O5P2 VCC I/O6P2 I/O7P2 N/C I/O0P3 I/O1P3 VCC I/O2P3 I/O3P3 I/O4P3 GND I/O5P3 I/O6P3 I/O7P3 VCC I/O0P4 I/P1P4 N/C
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
N/C N/C OEP2 BUSYP2 A0P1 A1P1 A2P1 A3P1 A4P1 A5P1 A6P1 A10P1 VCC A7P1 A8P1 A9P1 N/C CEP1 R/WP1 OEP1 BUSYP1 I/O0P1 I/O1P1 I/O2P1 I/O3P1 GND I/O4P1 I/O5P1 N/C N/C
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91
CEP2 R/WP2 N/C A9P2 A8P2 A7P2 A10P2 A6P2 A5P2 A4P2 A3P2 A2P2 A1P2 A0P2 N/C A0P3 A1P3 A2P3 A3P3 A4P3 A5P3 A6P3 A10P3 A7P3 A8P3 A9P3 N/C OEP3 CEP3 R/WP3
IDT7052PF PN120-1(4) 120-Pin Thin Quad Flatpack Top View(5)
90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
N/C N/C BUSYP3 A0P4 A1P4 A2P4 A3P4 A4P4 A5P4 A6P4 A10P4 GND A7P4 A8PR A9P4 N/C CEP4 R/WP4 OEP4 BUSYP4 GND I/O7P4 I/O6P4 I/O5P4 GND I/O4P4 I/O3P4 I/O2PR N/C N/C
2674 drw 04
3 6.42
IDT7052S/L High-Speed 2K x 8 FourPortTM Static RAM
Military, Industrial and Commercial Temperature Ranges
Pin Configurations(1,2)
Symbol A0 P1 - A10 P1 A0 P2 - A10P2 A0 P3 - A10 P3 A0 P4 - A10 P4 I/O0 P1 - I/O7 P1 I/O0 P2 - I/O7 P2 I/O0 P3 - I/O7 P3 I/O0 P4 - I/O7 P4 R/W P1 R/W P2 R/W P3 R/W P4 GND CE P1 CE P2 CE P3 CE P4 OE P1 OE P2 OE P3 OE P4 BUSY P1 BUSY P2 BUSY P3 BUSY P4 VCC Pin Name Address Line s - Port 1 Address Line s - Port 2 Address Line s - Port 3 Address Line s - Port 4 Data I/O - Port 1 Data I/O - Port 2 Data I/O - Port 3 Data I/O - Port 4 Read/Write - Port 1 Read/Write - Port 2 Read/Write - Port 3 Read/Write - Port 4 Ground Chip Enab le - Port 1 Chip Enab le - Port 2 Chip Enab le - Port 3 Chip Enab le - Port 4 Output Enab le - Port 1 Output Enab le - Port 2 Output Enab le - Port 3 Output Enab le - Port 4 Write Disab le - Port 1 Write Disab le - Port 2 Write Disab le - Port 3 Write Disab le - Port 4 Power
2674 tbl 01
Absolute Maximum Ratings(1)
Symbol VTERM(2) Rating Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature DC Output Current Commercial & Industrial -0.5 to +7.0 Military -0.5 to +7.0 Unit V
TBIAS TSTG IOUT
-55 to +125 -55 to +125 50
-65 to +135 -65 to +150 50
o
C C
o
mA
2674 tbl 02
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > VCC + 10%.
Maximum Operating Temperature and Supply Voltage(1, 2)
Grade Military Commercial Industrial Ambient Temperature -55OC to+125OC 0OC to +70OC -40 C to +85 C
O O
GND 0V 0V 0V
Vcc 5.0V + 10% 5.0V + 10% 5.0V + 10%
2674 tbl 04
NOTES: 1. This is the parameter TA. 2. Industrial temperature: for specific speeds, packages and powers, contact your sales office
NOTES: 1. All VCC pins must be connected to the power supply. 2. All GND pins must be connected to the ground supply
Recommended DC Operating Conditions
Symbol VCC Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Min. 4.5 0 2.2 -0.5
(1)
Typ. 5.0 0
____ ____
Max. 5.5 0 6.0
(2)
Unit V V V V
2674 tbl 05
Capacitance
Symbol CIN COUT
(1)
GND VIH
(TA = +25C, f = 1.0MHz) TQFP only
Parameter Input Capacitance Output Capacitance Conditions(2) VIN = 0V VOUT = 0V Max. 9 10 Unit pF pF
2674 tbl 03
VIL
0.8
NOTES: 1. VIL > -1.5V for pulse width less than 10ns. 2. VTERM must not exceed Vcc + 10%.
NOTES: 1. This parameter is determined by device characterization but is not production tested. 2. 3dV references the interpolated capacitance when the input and the output signals switch from 0V to 3V or from 3V to 0V.
4 6.42
IDT7052S/L High-Speed 2K x 8 FourPortTM Static RAM
Military, Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1,5,6) (VCC = 5.0V 10%)
7052X20 Com'l Only Symbol ICC1 Parameter Operating Power Supply Current (All Ports Active) Condition CE = VIL Outputs Open f = 0(3) Version COM'L. MIL. & IND. COM'L. MIL. & IND. COM'L. MIL. & IND. ISB1 Full Standby Current (All Ports - All CMOS Level Inputs) All Ports CE > VCC - 0.2V VIN > VCC - 0.2V or VIN < 0.2V, f = 0(3) COM'L. MIL. & IND. S L S L S L S L S L S L S L S L Typ.(2) 150 150
____ ____
7052X25 Com'l & Military Typ.(2) 150 150 150 150 225 195 225 195 45 40 45 40 1.5 0.3 1.5 0.3 Max. 300 250 360 300 350 305 400 340 85 70 115 85 15 1.5 30 4.5
7052X35 Com'l & Military Typ.(2) 150 150 150 150 210 180 210 180 40 35 40 35 1.5 0.3 1.5 0.3 Max. 300 250 360 300 335 290 395 330 75 60 110 80 15 1.5 30 4.5
2674 tbl 06
Max. 300 250
____ ____
Unit mA
ICC2
Dynamic Operating Current (All Ports Active)
CE = VIL Outputs Open f = fMAX(4)
240 210
____ ____
370 325
____ ____
mA
ISB
Standby Current (All Ports - TTL Level Inputs)
CE = VIH f = fMAX(4)
70 60
____ ____
95 80
____ ____
mA
1.5 0.3
____ ____
15 1.5
____ ____
mA
NOTES: 1. 'X' in part number indicates power rating (S or L). 2. VCC = 5V, TA = +25C and are not production tested. 3. f = 0 means no address or control lines change. 4. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using "AC Test Conditions" of input levels of GND to 3V. 5. For the case of one port, divide the appropriate current above by four. 6. Industrial temperature: for specific speeds, packages and powers contact your sales office.
DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VCC = 5.0V 10%)
7052S Symbol |ILI| |ILO| VOL VOH Parameter Input Leakage Current(1) Output Leakage Current Output Low Voltage Output High Voltage Test Conditions VCC = 5.5V, VIN = 0V to VCC CE = VIH, VOUT = 0V to VCC IOL = 4mA IOH = -4mA Min.
___
7052L Max. 10 10 0.4
___
Min.
___
Max. 5 5 0.4
___
Unit A A V V
2674 tbl 07
___
___
___
___
2.4
2.4
NOTE: 1. At Vcc < 2.0V input leakages are undefined.
5 6.42
IDT7052S/L High-Speed 2K x 8 FourPortTM Static RAM
Military, Industrial and Commercial Temperature Ranges
(L Version Only) VLC = 0.2V, VHC = VCC - 0.2V
Symbol VDR ICCDR Parameter VCC for Data Retention Data Retention Current
Data Retention Characteristics Over All Temperature Ranges(4)
Test Condition VCC = 2V CE > VHC VIN > VHC or < VLC tCDR tR
(3) (3)
Min. 2.0
Typ.(1)
___
Max.
___
Unit V A
Com'l. Mil. & Ind.
___
25 25
___
600 1800
___
___
Chip Deselect to Data Retention Time Operation Recovery Time
0 tRC
(2)
ns ns
2674 tbl 08a
___
___
NOTES: 1. VCC = 2V, TA = +25C 2. tRC = Read Cycle Time 3. This parameter is guaranteed but not production tested. 4. Industrial temperature: For other speeds, packages and powers contact your sales office.
Low VCC Data Retention Waveform
DATA RETENTION MODE VCC tCDR CE VDR VIH VIH
2674 drw 05
4.5V
VDR 2V
4.5V tR
AC Test Conditions
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 5ns Max. 1.5V 1.5V Figures 1 and 2
2674 tbl 08b
, 2674 drw 06
5V 893 DATAOUT 347 30pF DATAOUT 347
5V 893
5pF*
Figure 1. AC Output Test Load
Figure 2. Output Test Load (for tLZ, tHZ, tWZ, tOW) *Including scope and jig
6 6.42
IDT7052S/L High-Speed 2K x 8 FourPortTM Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature and Supply Voltage(3,4)
7052X20 Com'l Only Symbol READ CYCLE tRC tAA tACE tAOE tOH tLZ tHZ tPU tPD Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Output Hold from Address Change Output Low-Z Time
(1,2)
7052X25 Com'l & Military Min. Max.
7052X35 Com'l & Military Min. Max. Unit
Parameter
Min.
Max.
20
____
____
25
____
____
35
____
____
ns ns ns ns ns ns ns ns ns
2674 tbl 09
20 20 10
____
25 25 15
____
35 35 25
____
____
____
____
____
____
____
0 5
____
0 5
____
0 5
. ____
____
____
____
Output High-Z Time(1,2) Chip Enable to Power Up Time (2) Chip Disable to Power Down Time
(2)
12
____
15
____
15
____
0
____
0
____
0
____
20
25
35
NOTES: 1. Transition is measured 200mV from Low or High-Impedance voltage with the Output Test Load (Figure 2) 2. This parameter is guaranteed by device characterization but is not production tested. 3. 'X' in part number indicates power rating (S or L) 4. Industrial temperature: for specific speeds, packages and powers contact your sales office.
Timing Waveform of Read Cycle No. 1, Any Port(1)
tRC ADDRESS tAA tOH DATAOUT
NOTES: 1. R/W = VIH, OE = VIL and CE = VIL.
tOH DATA VALID
2674 drw 07
PREVIOUS DATA VALID
Timing Waveform of Read Cycle No. 2, Any Port(1,2)
tACE CE tAOE OE tLZ DATAOUT tLZ tPU ICC CURRENT ISB
NOTES: 1. R/W = VIH for Read Cycles. 2. Addresses valid prior to or coincident with CE transition LOW.
tHZ
tHZ VALID DATA tPD
50%
50%
2674 drw 08
7 6.42
IDT7052S/L High-Speed 2K x 8 FourPortTM Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature and Supply Voltage(7,8)
7052X20 Com'l Only Symbol WRITE CYCLE tWC tEW tAW tAS tWP tWR tDW tHZ tDH tWZ tOW tWDD tWDD Write Cycle Time Chip Enable to End-of-Write (3) Address Valid to End-of-Write Address Set-up Time Write Pulse Width
(3)
7052X25 Com'l & Military Min. Max.
7052X35 Com'l & Military Min. Max. Unit
Parameter
Min.
Max.
20 15 15 0 15 0 15
____
____
25 20 20 0 20 0 15
____
____
35 30 30 0 30 0 20
____
____
ns ns ns ns ns ns ns ns ns ns ns ns ns
____
____
____
____
____
____
____
____
____
____
____
____
Write Recovery Time Data Valid to End-of-Write Output High-Z Time(1,2) Data Hold Time Write Enable to Output in High-Z Output Active from End-of-Write Write Pulse to Data Delay(4) Write Data Valid to Read Data Delay (4)
(1,2)
____
____
____
____
____
____
15
____
15
____
15
____
0
____
0
____
0
____
12
____
15
____
15
____
(1,2)
0
____
0
____
0
____
35 30
45 35
55 45
____
____
____
BUSY INPUT TIMING tWB tWH Write to BUSY(5) Write Hold After BUSY
(6)
0 15
____
0 15
____
0 20
____
ns ns
2674 tbl 10
____
____
____
NOTES: 1. Transition is measured 200mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization but is not production tested. 3. If OE = VIL during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the bus for the required tDW. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. Specified for OE = VIH (refer to "Timing Waveform of Write Cycle", Note 8). 4. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read". 5. To ensure that the write cycle is inhibited on port "A" during contention from Port "B". Port "A" may be any of the four ports and Port "B" is any other port. 6. To ensure that a write cycle is completed on port "A" after contention from Port "B". Port "A" may be any of the four ports and Port "B" is any other port. 7. 'X' in part number indicates power rating. 8. Industrial temperature: for specific speeds, packages and powers contact your sales office.
8 6.42
IDT7052S/L High-Speed 2K x 8 FourPortTM Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(5,8)
tWC ADDRESS tAS
(6)
OE
(9)
tAW CE
tWR
(3)
tWP (2) R/W tLZ DATAOUT
(4)
tHZ
(7)
tWZ (7) tOW
(4)
tHZ
(7)
tDW DATAIN
tDH
2674 drw 09
Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1, 5)
tWC ADDRESS tAW CE
(9) (3)
tAS R/W
(6)
tEW(2)
tWR
tDW DATAIN
tDH
2674 drw 10
NOTES: 1. R/W or CE = VIH during all address transitions. 2. A write occurs during the overlap (tEW or tWP) of a CE = VIL and a R/W = VIL. 3. tWR is measured from the earlier of CE or R/W = VIH to the end of write cycle. 4. During this period, the I/O pins are in the output state, and input signals must not be applied. 5. If the CE = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal is asserted last, CE or R/W. 7. Transition is measured 200mV from Low or High-impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed but is not production tested. 8. If OE = VIL during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the bus for the required tDW. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
9 6.42
IDT7052S/L High-Speed 2K x 8 FourPortTM Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Port-to-Port Read(1,2,3)
tWC ADDR"A" R/W"A" tDW DATAIN"A" VALID tDH MATCH tWP
ADDR"B"
MATCH
tWDD DATA"B" tDDD NOTES: 1. Assume BUSY input = VIH and CE = VIL for the writing port. 2. OE = VIL for the reading ports. 3. All timing is the same for left and right ports. Port "A" may be either of the four ports and Port "B" is any other port.
VALID
2674 drw 11
Timing Waveform of Write with BUSY Input
tWP R/W"A" tWB BUSY"B" tWH
R/W"B"
NOTES: 1. BUSY is aserted on Port "B" blocking R/W"B" until BUSY"B" goes HIGH.
(1)
, 2674 drw 12
Functional Description
The IDT7052 provides four ports with separate control, address, and I/O pins that permit independent access for reads or writes to any location in memory. These devices have an automatic power down feature controlled by CE. The CE controls on-chip power down circuitry that permits the respective port to go into standby mode when not selected (CE = VIH). When a port is enabled, access to the entire memory array is permitted. Each port has its own Output Enable control (OE). In the read mode, the port's OE turns on the output drivers when set LOW. READ/ WRITE conditions are illustrated in the table below.
Truth Table I Read/Write Control(3)
Any Port(1) R/W X X L H X CE H H L L X OE X X X L H D0-7 Z Z DATAIN DATAOUT Z Function Port Deselected: Power-Down CEP1=CEP2=CEP3=CEP4=VIH Power Down Mode ISB or ISB1 Data on port written into memory (2) Data in memory output on port Outputs Disabled
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NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care, "Z "= High Impedance 2. If BUSY = VIL, write is blocked. 3. For valid write operation, no more than one port can write to the same address location at the same time.
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IDT7052S/L High-Speed 2K x 8 FourPortTM Static RAM
Military, Industrial and Commercial Temperature Ranges
Ordering Information
IDT XXXX Device Type A Power 999 Speed A Package A Process/ Temperature Range Blank I(1) B G PQF PF 20 25 35 L S 7052 Commercial (0C to +70C) Industrial (-40C to +85C Military (-55C to +125C) Compliant to MIL-PRF-38535 QML 108-Pin Pin Grid Array (G108-1) 132-Pin Plastic Quad Flatpack (PQ132-1) 120-Pin Thin Quad Plastic Flatpack (PN120-1) Commercial Only Commercial & Military Commercial & Military Low Power Standard Power 16K (2K x 8) FourPort RAM
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Speed in nanoseconds
NOTE:
1. Industrial temperature range is available. For specific speeds, packages and powers contact your sales office.
Datasheet Document History
1/18/99: Initiated datasheet document history Converted to new format Cosmetic typographical corrections Added additional notes to pin configurations Changed drawing format Page1 Corrected DSC number
6/4/99:
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for Tech Support: 831-754-4613 DualPortHelp@idt.com
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